1. Field of Invention
The present invention relates generally to a semiconductor device. More particularly to a nitride read only memory (NROM) cell structure.
2. Description of Related Art
Nitride Read-Only-Memory (NROM) device is well known to be n-channel MOSFET memory device comprising a capturing or trapping dielectric material, for example a silicon nitride layer sandwiched between two silicon oxide layers (ONO). The charge is stored in the nitride layer located over the channel region, providing charge retention mechanism for programming the memory cell, while the silicon oxide layers which sandwiches the nitride layer is to avoid any tunneling of this charge. When programming voltages are provided to the source, the drain and the gate, electrons flows towards the drain as a result, some hot electrons penetrate through the lower section of silicon oxide, and are then collected and concentrated in the nitride layer. The concentrated charge in the nitride layer will significantly raise the threshold voltage of the portion of the channel region to a level higher than the threshold voltage of the remaining portion of the channel. When concentrated charge is present the memory cell is said to be programmed, and under this condition, the raised threshold voltage of the memory cell does not permit the memory cell to be in a conductive state during reading. On the other hand, if concentrated charge is not present in the nitride layer, then read voltage on gate can overcome the much lower threshold and accordingly, channel becomes inverted and hence, conductive.
The use of NROM is preferred over the conventional read only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM). electrically erasable programmable ROM (EEPROM) and flash EEPROM because NROM is programmable by using channel hot electron injection to trap charge in the nitride layer sandwiched between two silicon oxide layers through the channel region, thereby reducing the programming time compared to the programming time required in the conventional PROM devices. Further, in a conventional device (for example, PROM) the time required to erase a program is much greater than the programming time, thus the total time required for the erasing and programming is greatly increased.
It is well known design rule that in order to achieve faster, smaller, and more densely packed integrated circuit device in semiconductor device manufacturing, the transistor size including the gate length and the channel length should be reduced. However, a stage is reached where the gate length and the channel length cannot be reduced beyond a critical value which would otherwise increase the parasitic source/drain junction capacitance of the device, resulting in adverse effects what is commonly known as short channel effects such as, hot carrier damage, and the possibility of punch-through between the source/drain regions, which would have an adverse effect on the device performance. Therefore, the size reduction of the transistors for further integration of the semiconductor device is limited due to the short channel length.
One way to improve integrated circuit device performance is to reduce the junction capacitance of transistor. To reduce junction capacitance, the channel length has to be large enough to avoid short channel effects. But a large channel length would limit the size reduction of the transistor beyond the critical value, as described above, thereby limiting the integration of the semiconductor device.
Accordingly, it is highly desirable to provide a method of fabricating a MOSFET structure having reduced size and while maintaining good device characteristics.
Accordingly, it is an object of the present invention is to provide a method for fabricating a NROM structure where the size reduction is not limited to the channel length.
Another object of the present invention is to provide a method for fabricating a NROM structure, wherein the channel is disposed along vertical direction. Therefore, in this scheme channel length would not limit the reduction of the device size.
Yet another object of the present invention is to provide a method for fabricating a NROM structure having a reduced junction capacitance so that the performance of the NROM device is improved.
Yet another object of the present invention is to provide a method for fabricating a NROM structure having a desired channel length so that the junction capacitance of the device can be effectively adjusted so that a device with a desired performance can be achievable.
In accord with above objects and other advantages, the present invention provides a method for fabricating a vertical nitride read-only-memory unit, comprising, providing a substrate, forming a trench in the substrate, performing an ion implantation into the substrate to form a first source/drain region and a second source/drain region within the substrate in the upper corners of the trench, and to form a common source/drain region in the substrate at a bottom of the trench. Next, forming a trapping layer over the substrate and the trench and forming a gate conducting layer over the substrate and filling the trench.
An aspect of the present invention is that because the NROM device of the present invention is a vertical device, therefore, the area occupied by the vertical NROM device is substantially smaller compared to the conventional NROM device, which is a horizontal structure. Therefore higher integration of memory device can be realized.
Another aspect of the present invention is that because the NROM device of the present invention is a vertical structure, therefore, the channel is also disposed in a vertical direction. Therefore the bit lines can be disposed along the X direction. This allows size reduction of the NROM cell.
Yet another aspect of the present invention is that because the NROM device of the present invention is a vertical structure, therefore, the channel is also disposed in a vertical direction. Therefore the channel length can be adjusted by adjusting the depth of the trench, thus a channel length of desired length can be effectively formed for a desired (reduced) junction capacitance. Therefore the undesired effects due to short channel effects such as hot carrier damage or punch-through effects can be effectively avoided thereby, good device characteristics can be maintained.
Yet another aspect of the present invention is that because the reduced junction capacitance the RC delay time can be effectively decreased. Therefore the operation speed of the device is effectively increased, thereby the device performance can be substantially improved.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.